JD0New Contributor4 years agoCyclone V GX - HARD IP PCIe - Reference Clock Hello, please I want to use Cyclone V GX (5CGXFC5C6F23C7) and 2 pcs of its HARD IP PCIe. We have on PCB routed signals to two transceivers (GXB_0 and GXB_5) and clock signal to REFCLK1, but with b...Show More
SengKok_L_IntelRegular Contributor4 years agoHi, Yes, this is unable to use the output of the PLL as the PCIe reference clock.
Recent DiscussionsUser controlled burst refreshCascaded Avalon Stream Multiplexer in Platform Design does not forward valid data packetsF-Tile PCIe Root port - rx_st_hdr_oTeransceiver & FPGAWhy does Fitter show "Dedicated Pin" as "Reference Clock Source by" for downstream PLL in cascade?Solved