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rsing108's avatar
rsing108
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

can't program stratix 10 GX with pcie hard ip+ example design

I am getting the following errors while programming the Stratix 10 GX board with the PCIE hard ip+ example design. quartus_pro 19.4 Error (18950): Device has stopped receiving configuration data ...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


To better understanding the problem, could you please provide the following info?


  1. How do you generate the example design? Is this from the IP GUI?
  2. Did you connect the board to a proper setup, where there is PCIe reference clock coming to the FPGA end point?


Regards -SK