Forum Discussion

rsing108's avatar
rsing108
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

can't program stratix 10 GX with pcie hard ip+ example design

I am getting the following errors while programming the Stratix 10 GX board with the PCIE hard ip+ example design. quartus_pro 19.4 Error (18950): Device has stopped receiving configuration data ...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Thanks for the reply.


Did you connect the PCIe End point to the root port with the proper PCIe reference clock before you program the SOF? If without a proper PCIe reference clock, you will fail the programming.


Regards -SK


  • rsing108's avatar
    rsing108
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi @SengKok_L_Intel ,

    I did not find any such step in the manual so I have not specifically defined it, but shouldn't it be already done while generating the example design? Also does this attachment help or should I provide any other file? Sorry, I am not much familiar with this IP.