gate timing spec on 40nm FPGA

Hi,

I'm afraid I don't have the actual figures for you but the specs you want are dependent on quite a few variables.

Firstly if you are using measuring these values in a design they may change depending on where where the logic is placed on the FPGA. e.g. setup and hold time will vary by the difference of how far the signals have to travel from where they are asserted. Temperature and process variation as well as the speed grade of the FPGA will have an effect so there is probably no one real answer. Although I'm sure people involved with Altera could probably give you a better idea.

Just my 2 cents!

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Hi everybody,

Does anyone know what is the delay time of a "not" gate in 40nm technology?

And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latch ? on which FPGA ?

Also what is the minimum Time Setup and Time Hold for a single FlipFlop ? on which FPGA ?

Big thanks for who may give me ansers to my questions!!!!!!!:p ;) :)

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Hi Shalom,

what is the question behind your post ? Can you expalin a little bit more about your intentions?

Kind regards

GPK

Hi everybody,

First of all, thank you for your answers.

Behind my post I am trying to find how to delay a signal by 40-100 ps, so I make it travel throw one or more "not" gates (who have a small delay).

For this I need to know what is approximatively the delay of one "not" gate on FPGA.

Also I need to know what is the minimum pulse width for a clock input register on 40nm FPGA

thank's for answers

Shalom

Hi Shalom,

Passing a signal through more gates will give you a delay, but not always the same delay for the reasons given in my first post. You may find that by chance it works for you, but any change to your source code and after a new place and route the results will almost certainly be different.

To achieve what you want, you should use the timequest timing analyzer or classic if you haven't learned timequest and put in place your various constraints to achieve the timing you want.

If you give some details as to what exactly you are trying to implement and why then I think people will be able to help you out more.

Shalon,

due to several reasons, trying to delay a signal by adding logic cells in a FPGA is a terribly bad idea.

Not only the delay of the logic cell will vary with process and temperature but you'll also have interconnect delay, which too will vary with process, temperature and your design.

These add up into the >1 ns range easily.

As Ardni, I sugest you provide with more information about what you're trying to do.

Hi everybody,

Afters those requests, I want to delay a clock(~ 100 KHz) by a few ps(between 40 to 100ps) many times in order to have many clocks, that are delayed each one from the other, by few ps.

I would like, but I cannot provide more information...

Also what is the minimum clock pulse width on one register or one Flip-flop on 40nm FPGA ??

Many thank's for any answers.

Shalom

Shalom,

To achieve phase shift between clocks, the best option is to use the PLL in the Altera megafucntion library. You can easily configure it to implement a phase shift between the different clock outputs.

Have a look at it and let us know if it will do the job for you. It´s quite simple to understand and configure.

Also regarding the minimum clock pulse width, its impossible to say for the reasons given earlier. Due to temperature, process variation, speed grade etc you cannot get a reliable number that applies all the time.

Your timing analyzer will give you the max frequency acheivable for a givien circuit and from that you can obtain what the minimum pulse width is.

It´s not normal to want to know the minimum pulse width for one FF. Instead you should be looking at the critical data paths throughout your design and thinking about it on that (higher) level.

Understanding the data given by the timing analyzer will give you a better understanding of things

Dear shalom,

I'm afraid what you're trying to do is somewhat not feasible with an FPGA.

With an Altera FPGA PLL, the closest you can do is to generate 100 kHz clocks and control it's phase in 194ps steps.

And then you can't control the clocks' distribution delay, from the PLL to the clocks' users, with a 40-100 ps precision.

Just to make sure though, can you confirm you want 40-100ps, not 40-100 ns?

First i confirm that the delay is 40-100ps. And thanks everybody for answers, its for me a big help.

For design of delay, the uses of PLL its a good idea. Maybe I will try to start with this, maybe with higher clocks I will achieve a delay closer to the desired range 40-100ps - thanks to rbugalho.

For the minimum clock pulse width: My question is here yet: For a given max frequency (Fmax) achievable for a given circuit, this implies that the minimum period is 1/Fmax, is this implies that the minimum clock pulse width is 1/(2*Fmax) or can be shorter ?? if yes how shorter can be??

Shalom