gate timing spec on 40nm FPGA

Shalon,

due to several reasons, trying to delay a signal by adding logic cells in a FPGA is a terribly bad idea.

Not only the delay of the logic cell will vary with process and temperature but you'll also have interconnect delay, which too will vary with process, temperature and your design.

These add up into the >1 ns range easily.

As Ardni, I sugest you provide with more information about what you're trying to do.