gate timing spec on 40nm FPGA

Hi Shalom,

Passing a signal through more gates will give you a delay, but not always the same delay for the reasons given in my first post. You may find that by chance it works for you, but any change to your source code and after a new place and route the results will almost certainly be different.

To achieve what you want, you should use the timequest timing analyzer or classic if you haven't learned timequest and put in place your various constraints to achieve the timing you want.

If you give some details as to what exactly you are trying to implement and why then I think people will be able to help you out more.