gate timing spec on 40nm FPGA

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Hi everybody,

Does anyone know what is the delay time of a "not" gate in 40nm technology?

And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latch ? on which FPGA ?

Also what is the minimum Time Setup and Time Hold for a single FlipFlop ? on which FPGA ?

Big thanks for who may give me ansers to my questions!!!!!!!:p ;) :)

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Hi Shalom,

what is the question behind your post ? Can you expalin a little bit more about your intentions?

Kind regards

GPK