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Altera_Forum
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16 years ago

gate timing spec on 40nm FPGA

Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi everybody,

First of all, thank you for your answers.

Behind my post I am trying to find how to delay a signal by 40-100 ps, so I make it travel throw one or more "not" gates (who have a small delay).

For this I need to know what is approximatively the delay of one "not" gate on FPGA.

Also I need to know what is the minimum pulse width for a clock input register on 40nm FPGA

thank's for answers

Shalom