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Honored Contributorgate timing spec on 40nm FPGA
Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latc...
Altera_ForumHonored Contributor
Honored ContributorDear shalom,
I'm afraid what you're trying to do is somewhat not feasible with an FPGA. With an Altera FPGA PLL, the closest you can do is to generate 100 kHz clocks and control it's phase in 194ps steps. And then you can't control the clocks' distribution delay, from the PLL to the clocks' users, with a 40-100 ps precision. Just to make sure though, can you confirm you want 40-100ps, not 40-100 ns?
