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Altera_Forum
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16 years ago

gate timing spec on 40nm FPGA

Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latc...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Hi everybody,

Afters those requests, I want to delay a clock(~ 100 KHz) by a few ps(between 40 to 100ps) many times in order to have many clocks, that are delayed each one from the other, by few ps.

I would like, but I cannot provide more information...

Also what is the minimum clock pulse width on one register or one Flip-flop on 40nm FPGA ??

Many thank's for any answers.

Shalom