gate timing spec on 40nm FPGA

Also regarding the minimum clock pulse width, its impossible to say for the reasons given earlier. Due to temperature, process variation, speed grade etc you cannot get a reliable number that applies all the time.

Your timing analyzer will give you the max frequency acheivable for a givien circuit and from that you can obtain what the minimum pulse width is.

It´s not normal to want to know the minimum pulse width for one FF. Instead you should be looking at the critical data paths throughout your design and thinking about it on that (higher) level.

Understanding the data given by the timing analyzer will give you a better understanding of things