gate timing spec on 40nm FPGA

Hi,

I'm afraid I don't have the actual figures for you but the specs you want are dependent on quite a few variables.

Firstly if you are using measuring these values in a design they may change depending on where where the logic is placed on the FPGA. e.g. setup and hold time will vary by the difference of how far the signals have to travel from where they are asserted. Temperature and process variation as well as the speed grade of the FPGA will have an effect so there is probably no one real answer. Although I'm sure people involved with Altera could probably give you a better idea.

Just my 2 cents!