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Altera_Forum
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16 years ago

gate timing spec on 40nm FPGA

Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latc...
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Altera_Forum
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15 years ago

Shalom,

To achieve phase shift between clocks, the best option is to use the PLL in the Altera megafucntion library. You can easily configure it to implement a phase shift between the different clock outputs.

Have a look at it and let us know if it will do the job for you. It´s quite simple to understand and configure.