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Altera_Forum
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16 years ago

gate timing spec on 40nm FPGA

Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latc...
Altera_Forum's avatar
Altera_Forum
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15 years ago

First i confirm that the delay is 40-100ps. And thanks everybody for answers, its for me a big help.

For design of delay, the uses of PLL its a good idea. Maybe I will try to start with this, maybe with higher clocks I will achieve a delay closer to the desired range 40-100ps - thanks to rbugalho.

For the minimum clock pulse width: My question is here yet: For a given max frequency (Fmax) achievable for a given circuit, this implies that the minimum period is 1/Fmax, is this implies that the minimum clock pulse width is 1/(2*Fmax) or can be shorter ?? if yes how shorter can be??

Shalom