Recent Content
Why do setup and minimum pulse width timing violations occur in the LVDS SERDES IP Design Example?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1 and earlier, you may encounter setup and minimum pulse width timing violations in the LVDS SERDES IP Design Example. This issue is caused by an incorrect value of the vco_data_rate_ratio parameter used in the LVDS SERDES IP, which leads to improper timing constraints and resulting violations. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, follow the steps below: Step 1: In the auto-generated file intel_lvds_core10_ph2_hw_ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sv, Original: .vco_data_rate_ratio(0), Change to: .vco_data_rate_ratio(<correct_vco_data_rate_ratio>), Step 2: In the auto-generated file ed_synth_intel_lvds_0_example_design_example_design_intel_lvds_core10_ph2_191_<string>.sdc, add this SDC constraint set ip_params(vco_data_rate_ratio) <correct_vco_data_rate_ratio> Step 3: Re-compile the design The correct vco_data_rate_ratio parameter value based on the LVDS SERDES IP data rate (Mbps) shown in table below: Use the appropriate vco_data_rate_ratio based on the LVDS SERDES IP data rate: data_rate >= 600 Mbps 1 600 Mbps > data_rate >= 300 Mbps 2 data_rate < 300 Mbps 4 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Related IP Core: LVDS SERDES IPWhy does the Agilex® 5 FPGA Hard Processor System hang during ACCT IP operations when translating AXI4 to ACE5‑LITE?
Description Due to an issue in Quartus® Prime Pro Edition Software version 25.1, the readdatareordering_depth property of the ACCT IP AXI4 interface is not configured correctly. As a result, the interconnect is not set up to handle out‑of‑order responses. In this scenario, the Agilex® 5 FPGA Hard Processor System (HPS) may issue out‑of‑order responses during ACCT IP operations when translating AXI4 transactions to ACE5‑LITE. Because the interconnect is not configured to accommodate this behavior, the system may hang. Resolution This issue is scheduled to be fixed in Quartus® Prime Pro Edition Software version 26.1.Why does the Nios® V processor without data cache hang during a flash read operation using the Generic Serial Flash Interface (GSFI) IP HAL driver?
Description When performing a read operation on a flash device using the GSFI IP HAL driver, a Nios® V processor configured without a data cache may hang and stop functioning correctly due to an issue in the HAL driver. The HAL driver attempts to flush the data cache even when no data cache is present. This incorrect behavior places the processor into a non-deterministic state, which can cause the system to freeze. Resolution To work around this issue, update the following line in the intel_gsfi_read() function. Original: alt_dcache_flush_no_writeback((alt_u8*)qspi_flash_info->data_base + offset, length); Change to: #if ALT_CPU_DCACHE_SIZE > 0 alt_dcache_flush_no_writeback((alt_u8*)qspi_flash_info->data_base + offset, length); #endif This modification ensures that the data cache flush operation is performed only when a data cache is present. This issue will be fixed in a future Quartus® Prime Software release.Why does the read/write HAL API fail when the access length reaches the last byte of flash memory when using the Generic Serial Flash Interface (GSFI) IP HAL driver?
Description When performing a read or write operation on a flash memory device using the GSFI IP HAL read/write API, the API may incorrectly return an EINVAL error code. This issue occurs because the operation end address is miscalculated. As a result, the GSFI IP HAL API incorrectly determines that the operation end address exceeds the valid flash memory range and flags the access length as invalid. For example, when reading or writing the entire 1 GiB flash device, the operation reaches the last byte with an access length of 2147483648 bytes. In this case, the GSFI IP HAL API miscalculates the operation end address as 0x80000000, which exceeds the flash end address of 0x7FFFFFFF. Consequently, the access length is incorrectly treated as invalid, and a false EINVAL error code is returned. This issue does not occur when reading from or writing to other addresses that do not include the last byte of the flash memory. a { text-decoration: none; color: #464feb; } tr th, tr td { border: 1px solid #e6e6e6; } tr th { background-color: #f5f5f5; } Resolution To work around this issue, update the following line in the intel_gsfi_validate_read_write_arguments() Original: end_address = start_address + length; Change to: end_address = start_address + length - 1; This correction ensures the calculated end address does not exceed the valid flash memory range. This issue will be fixed in a future Quartus® Prime Design Software release.Why does Quartus® Prime Standard Edition Software v24.1 hang and fail to close after using the Programmer?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 and later, the Quartus® Prime Standard Edition Software might become unresponsive and fail to close after running the Quartus® Prime Programmer on Windows* 10 environments. The typical sequence that triggers the hang is: Launch the Quartus® Prime Standard Edition Software. Launch the Quartus® Prime Programmer from within the Quartus® Prime Standard Edition Software and complete programming. Close the Quartus® Prime Programmer. Attempt to close the Quartus® Prime Standard Edition Software. Result: Windows shows “Not Responding” and the application must be forcibly terminated. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 24.1, download and install the patch below: This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Why does an SDI hardware failure occur in single‑rate HD‑SDI parallel loopback without an external VCXO at 1280×720p24 across all FPGA device families?
Description Due to an issue in Quartus® Prime Pro Edition Software version 26.1 and earlier, an SDI hardware failure may be observed when using the Single‑Rate HD‑SDI Parallel Loopback design without an external VCXO and selecting the 1280 × 720p24 video standard on all SDI‑supported FPGA device families. This issue does not affect multi‑rate or triple‑rate HD modes. Resolution This issue is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. For users who must remain on Quartus® version 26.1 or earlier, use the following workaround: Regenerate the design using Quartus® Prime Pro Edition Software version 26.1.1 or later. In your target project, replace the entire pfd folder with the corresponding folder from the newly generated design. The updated PFD module can be found at: <Your_Design_Folder>/rtl/loopback/pfdWhy does the Ethernet link fail to come up during the U‑Boot stage after reboot on the Agilex® 5 FPGA 013B Dev Kit GSRD HPS?
Description Due to an issue in the Quartus® Prime Pro Edition software version 25.3.1 GSRD release for the Agilex® 5 FPGA 013B Development Kit, the Ethernet link may fail to initialize during the U‑Boot stage after a reboot. When the dhcp command is executed, the Ethernet connection does not come up successfully and the following error message is displayed: Resolution This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. Additional Information This issue occurs only when a reboot is performed after a successful power‑on. During the initial power‑on boot, the problem does not occur because the operating system uses a generic Ethernet driver. The issue arises because the Micrel PHY driver is not enabled by default in the U‑Boot configuration, causing the Ethernet link to fail during subsequent boot cycles.Why does the MIPI DSI‑2 FPGA IP design example fail when programming the FPGA on the Agilex® 3 FPGA and SoC C‑Series Development Kit?
Description Due to an issue in Quartus® Prime Pro Edition software version 26.1, users may encounter a failure when programming the FPGA with the .sof file generated by the MIPI DSI‑2 IP Design Example for the Agilex® 3 FPGA and SoC C‑Series Development Kit. This issue occurs because the design example generation script incorrectly maps the selected Agilex 3 development kit to an unintended target board. When configuring the FPGA using the Quartus Programmer, the following error may be reported: Error(18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0xXX Additionally, the FPGA part number shown in the generated example design may not match the FPGA device on the selected development kit. Resolution To work around this issue in Quartus® Prime Pro Edition software version 26.1, follow the steps below to generate the MIPI DSI‑2 IP Design Example for the correct Agilex® 3 FPGA device. 1. Open the Design Example Tab In the Quartus Prime Pro Edition software, open the MIPI DSI‑2 IP. Navigate to the Parameters window and ensure that the Design Example tab is selected at the top of the MIPI DSI‑2 IP GUI. 2. Select the Correct Target Board In the Target Development Kit section, open the Select Board drop‑down menu and choose the option that corresponds to your development kit, as shown in the table below: Development Kit Kit Part Number FPGA Part Number Target Board Option to Select Agilex® 3 FPGA and SoC C‑Series Development Kit DK‑A3W135BM16AEA A3CW135BM16AE6S Agilex® 3 FPGA C‑Series Development Kit Agilex® 3 FPGA C‑Series Development Kit DK‑A3Y135BM16AEA A3CY135BM16AE6S Agilex® 3 SoC C‑Series Development Kit Ensure that the selected target board option matches your development kit. 3. Generate the Design Example After selecting the correct target board option, click Generate Example Design and allow Quartus to complete the generation process. 4. Verify the FPGA Device Open the generated Quartus project and locate the device OPN in the Project Navigator. Verify that the device OPN (for example, A3CW135BM16AE6S) matches the FPGA part number listed for your development kit in the table above. If the device OPN matches, the design example has been generated correctly and can be programmed onto the FPGA. This problem affects only the target board selection mapping during design example generation for the Agilex® 3 FPGA and SoC C‑Series Development Kit. The MIPI DSI‑2 IP core and generated design examples are otherwise fully functional. This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why do I observe a bit mismatch on RX parallel data for the GTS CPRI PHY IP when selecting CPRI rates of 9.8 Gbps, 6 Gbps, or 2.4 Gbps?
Description Due to an issue with the FastSim model in Quartus® Prime Pro Edition software version 25.3.1, selecting CPRI speeds of 9.8 Gbps, 6 Gbps, or 2.4 Gbps may result in a bit mismatch on the RX parallel data. Resolution To work around this issue, comment out the following line in the files run_riviera.do, run_vcsmx.sh, and run_vsim.do located in the generated example design example_testbench folder: FAST_SIM_OPTIONS="+define+IP7521SERDES_UX_SIMSPEED" This issue is scheduled to be fixed in a future release of the Quartus Prime Pro Edition software.Why does a kernel panic occur when stress‑testing multiple TSN protocols on multi‑XGMAC?
Description Due to a problem in the Quartus® Prime Pro Edition Software version 25.3 and Quartus® Prime Pro Edition Software version 25.3.1, when running stress test in Multiple TSN Protocols on multi-XGMA user might observe Kernel Panic. Error message: [ 4264.470052] sp : ffff80008294bac0 [ 4264.470055] x29: ffff80008294bbe0 x28: ffff000801e60980 x27: 00000000000000e6 [ 4264.470067] x26: 0000000000000010 x25: ffff00080d6d23c8 x24: ffff800083d6de50 [ 4264.470077] x23: ffff000801e60980 x22: 0000000000000017 x21: 0000000000000000 [ 4264.470086] x20: ffff000801e62058 x19: 0000000000000000 x18: 0000000000000006 [ 4264.470094] x17: 7270202d20295542 x16: 5220736564756c63 x15: 0720072007200720 [ 4264.470103] x14: ffff8000821e5bd0 x13: 0720072007200720 x12: 0720072007200720 [ 4264.470112] x11: ffff8000821e5bd0 x10: 00000000000009ce x9 : ffff80008223dbd0 [ 4264.470121] x8 : 0000000000017fe8 x7 : 00000000fffff000 x6 : ffff80008223dbd0 [ 4264.470130] x5 : ffff800080ceb3d0 x4 : 0000000000000000 x3 : 000000000000c0c1 [ 4264.470139] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000801e62058 [ 4264.470148] Call trace: [ 4264.470151] _raw_spin_unlock_irqrestore+0x8/0x50 [ 4264.470160] __napi_poll+0x38/0x180 [ 4264.470169] net_rx_action+0x158/0x2c0 [ 4264.470177] handle_softirqs+0x100/0x244 [ 4264.470184] run_ksoftirqd+0x3c/0x4c [ 4264.470190] smpboot_thread_fn+0x20c/0x234 [ 4264.470198] kthread+0x110/0x120 [ 4264.470205] ret_from_fork+0x10/0x20 root@agilex5dka5e065bb32aes1:~# root@agilex5dka5e065bb32aes1:~# root@agilex5dka5e065bb32aes1:~# root@agilex5dka5e065bb32aes1:~# root@agilex5dka5e065bb32aes1:~# ip a 1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN group default qlen 1000 link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 inet 127.0.0.1/8 scope host lo valid_lft forever preferred_lft forever inet6 ::1/128 scope host noprefixroute valid_lft forever preferred_lft forever 2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000 link/ether 00:a0:c9:00:10:01 brd ff:ff:ff:ff:ff:ff permaddr 2a:e5:dc:bc:e7:88 inet 192.168.1.101/16 scope global eth0 valid_lft forever preferred_lft forever inet 224.10.10.11/24 scope global autojoin eth0 valid_lft forever preferred_lft forever inet 169.254.22.190/16 brd 169.254.255.255 scope global eth0 valid_lft forever preferred_lft forever inet6 fe80::2a0:c9ff:fe00:1001/64 scope link proto kernel_ll valid_lft forever preferred_lft forever 3: eth1: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc mq state UP group default qlen 1000 link/ether 00:a0:c9:00:10:07 brd ff:ff:ff:ff:ff:ff inet 192.169.1.101/16 scope global eth1 valid_lft forever preferred_lft forever inet 224.10.10.17/24 scope global autojoin eth1 valid_lft forever preferred_lft forever inet 169.254.79.97/16 brd 169.254.255.255 scope global eth1 valid_lft forever preferred_lft forever inet6 fe80::2a0:c9ff:fe00:1007/64 scope link proto kernel_ll valid_lft forever preferred_lft forever 4: eth2: <NO-CARRIER,BROADCAST,MULTICAST,UP> mtu 1500 qdisc mq state DOWN group default qlen 1000 link/ether 00:a0:c9:00:10:21 brd ff:ff:ff:ff:ff:ff permaddr 46:a5:ee:24:81:a3 inet 192.170.1.101/16 scope global eth2 valid_lft forever preferred_lft forever inet 224.10.10.23/24 scope global autojoin eth2 valid_lft forever preferred_lft forever inet6 2001:db8:0:aa03::2/64 scope global tentative valid_lft forever preferred_lft forever 6: sit0@NONE: <NOARP> mtu 1480 qdisc noop state DOWN group default qlen 1000 link/sit 0.0.0.0 brd 0.0.0.0 8: eth3: <BROADCAST,MULTICAST,DYNAMIC,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UP group default qlen 1000 link/ether 20:7b:d2:47:89:a8 brd ff:ff:ff:ff:ff:ff inet 10.244.237.7/22 metric 10 brd 10.244.239.255 scope global dynamic eth3 valid_lft 84431sec preferred_lft 84431sec inet6 fe80::227b:d2ff:fe47:89a8/64 scope link proto kernel_ll valid_lft forever preferred_lft forever root@agilex5dka5e065bb32aes1:~# [ 4390.473269] rcu: INFO: rcu_preempt self-detected stall on CPU [ 4390.479021] rcu: 0-....: (1 GPs behind) idle=2044/1/0x4000000000000000 softirq=332385/332386 fqs=83757 [ 4390.488388] rcu: (t=225792 jiffies g=647925 q=8385 ncpus=4) [ 4390.494034] CPU: 0 UID: 0 PID: 16 Comm: ksoftirqd/0 Not tainted 6.12.43-altera-gd4893c5f8111 #1 [ 4390.494042] Hardware name: SoCFPGA Agilex5 SoCDK (DT) [ 4390.494046] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--) [ 4390.494053] pc : _raw_spin_unlock_irqrestore+0x8/0x50 [ 4390.494068] lr : stmmac_napi_poll_rx+0xddc/0x10a8 [ 4390.494078] sp : ffff80008294bac0 [ 4390.494081] x29: ffff80008294bbe0 x28: ffff000801e60980 x27: 00000000000000e6 [ 4390.494094] x26: 0000000000000010 x25: ffff00080d6d23c8 x24: ffff800083d6de50 [ 4390.494103] x23: ffff000801e60980 x22: 0000000000000017 x21: 0000000000000000 [ 4390.494113] x20: ffff000801e62058 x19: 0000000000000000 x18: 0000000000000006 [ 4390.494122] x17: 7270202d20295542 x16: 5220736564756c63 x15: 0720072007200720 [ 4390.494131] x14: ffff8000821e5bd0 x13: 0720072007200720 x12: 0720072007200720 [ 4390.494139] x11: ffff8000821e5bd0 x10: 00000000000009ce x9 : ffff80008223dbd0 [ 4390.494148] x8 : 0000000000017fe8 x7 : 00000000fffff000 x6 : ffff80008223dbd0 [ 4390.494157] x5 : ffff800080ceb3d0 x4 : 0000000000000000 x3 : 000000000000c0c1 [ 4390.494165] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff000801e62058 [ 4390.494174] Call trace: Resolution This problem is resolved in Quartus® Prime Pro Edition Software 26.1 release.
