Forum Discussion
Occasional ContributorF2SDRAM fails to synthesize with custom logic
Hello guys,
We are using Agilex5 SOC F2SDRAM bridge.
I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-level ports. Does anyone know why this is happening? Also, is there an example design for F2SDRAM available? The GHRD is not very helpful since it only includes the JTAG master.
I suspect it might be a design issue, so I even removed the adapter and connected it only within Qsys, but it’s still acting up like this.
Does anyone know why this is happening even though everything is clearly declared and connected?
Hudson
18 Replies
HPark14Hello guys,
I've resolved this issue. Thank you for your support.
I created a r_out register and exported it to the top-level output
after that Quartus compilation succeeded.
SueC_AlteraContributor
Thanks for sharing your solution, HPark14!
- kbrunham_altera
New Contributor
Hi Hudson,
I believe the issue is your rdata_r is not preserved and thus gets optimized away. You may be able to see that in the synthesis report.
To preserve registers you can use the syn_preserve attribute on your declaration of the register.
- HPark14
Why does Quartus optimize?
RDATA is not connected.
tehjingy_AlteraRegular Contributor
Hi KoenVe
Unfortunately this is required. The expectation from the Quartus is to always have something connected to each F2SDRAM port (write and read).
- tehjingy_Altera
Hi HPark14
I would suggest to take a look at the way the termination of f2sdram signal in the following file in the example:
f2sdram_terminator_reg_256_hw.tcl
f2sdram_terminator_64_hw.tcl
- HPark14
"If more detailed messages were provided, I would debug it myself, but it only gives one-word answers like a parrot."
- HPark14
Here is my test module...
- tehjingy_Altera
Hi HPark14
This error behavior is expected because the F2SDRAM interface must be properly connected, as mentioned by my colleague, kbrunham_altera .
For reference, you can refer to the public design example below. It connects the unused F2SDRAM port to a no_periph subsystem, which effectively terminates the interface and satisfies this design requirement:
https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/tree/main/brd_altera_a5e065_premium_es/hw_base
I hope this helps.- HPark14
Example design is too difficult. If you patch it up with bridges and adapters, do you think users will like it? I'm uploading my user logic; I pasted it as is, but I keep getting RDATA errors. It's driving me crazy.
- HPark14
Thank you for your reply I am building the agilex5-demo designs. I will check the f2sdram reference design.
Thanks~
Archer_AlteraHi HPark14,
I suggest you to add one AXI bridge component between f2sdram interface of HPS and AXI master interface of your own module. Then this error will disappear. You may see other error but they may be solved easier.
Hope this is helpful.
Archer_Altera
KelvinK_AlteraHi Hudson,
To further debug, can you share the expended the error message regarding to the F2SDRAM error.
- kbrunham_altera
Hi Hudon,
The error Quartus is reporting is illegal connectivity of the RDATA interface. The device legality requires that this interface be connected to registers. I suspect that in your axi_master_tester component you are leaving rdata unconnected or tied off to a constant. What is needed is to create preserved registers that you connect to this interface.
You can see a similar example in https://github.com/altera-fpga/agilex5-demo-hps2fpga-interfaces/blob/main/custom_ip/h2f_termination_hw.tcl#L208
KoenVeIs it realy needed to have registers connected on the interface, isn't this just a limitation that is created by the check on rdata in the quartus software? Not anybody wants to read data from an interface, that doesn't make it an illegal AXI bus.
- HPark14
"If more detailed messages were provided, I would debug it myself, but it only gives one-word answers like a parrot."
