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HPark14's avatar
HPark14
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

F2SDRAM fails to synthesize with custom logic

Hello guys,  We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
Arm Processor
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HPark14's avatar
HPark14
Icon for Occasional Contributor rankOccasional Contributor
1 month ago

Hello guys,

 I've resolved this issue. Thank you for your support.

I created a r_out register and exported it to the top-level output 

after that Quartus compilation succeeded.

SueC_Altera's avatar
SueC_Altera
Icon for Contributor rankContributor
1 month ago

Thanks for sharing your solution, HPark14​!