Forum Discussion

HPark14's avatar
HPark14
Icon for New Contributor rankNew Contributor
13 days ago

F2SDRAM fails to synthesize with custom logic

Hello guys,  We are using Agilex5 SOC F2SDRAM bridge. I am trying to connect custom logic to the F2SDRAM, but it absolutely refuses to synthesize unless I export the signals directly to the top-lev...
Arm Processor
Hps Arch
HPark14's avatar
HPark14
Icon for New Contributor rankNew Contributor
12 days ago

Thank you for your reply I am building the agilex5-demo designs. I will check the f2sdram reference design.

Thanks~

Archer_Altera's avatar
Archer_Altera
Icon for Occasional Contributor rankOccasional Contributor
6 days ago

Hi HPark14​,

I suggest you to add one AXI bridge component between f2sdram interface of HPS and AXI master interface of your own module. Then this error will disappear. You may see other error but they may be solved easier.

Hope this is helpful.

Archer_Altera