Reset Release IP VHDL code not working

Hello,

I do not know what implementation is needed. I moved the RRIP into its own .vhd file and now my top-level file is riddled with errors. I simply cut and pasted all the RRIP code into a separate file and saved it into the same directory. I gave it its own architecture and begin statements. What else needs to be done? All the errors are coming up as part of something else not working (ghost errors I call them).

Thank you,

Drew

Hello,

I did not do it right? The component and entity have the same name. Perhaps I am not seeing what you are saying. Could you please tell me what lines are not right. I have a rr_ip and resetRelease component and instantiation. Do I not need both?

Thank you,

Drew

Hello,

I decided to just dump all the RRIP I had and start from scratch as the program was giving me a headache. I found out how to see the .vhd file in the RRIP and saw that I had a conflicting naming convention for the files. That was probably some of the problems. I am still going through the online training of Intel, but I have not gotten to everything yet. I see the .vhd file associated with the RRIP has and see that it has an entity that deals with the ninit_done port. I have re-written the reset release file with this new file in mind and the links you all have sent me. I thought I could get the code right, but I still am not getting it. I do not know why this is not clicking with me. I also see that I had somehow mixed up a port. Locked equals to locked, not the out clock. I do not know why I saw that. The code looks much cleaner now, but it is still riddled with errors. I should get this by now, but I am not. The code without the RRIP compiles without error but gets a severe warning of no RRIP in the program. At this point, I am hoping someone has an actual file for RRIP.

Thank you,

Drew

Hello,

The errors I get are coming from extraneous things. The errors are being caused by one error in one file that infects other files. The code that I know works as it compiles is now erroring out because of something in another file. I am attaching the clockdiv file, so you know what it is. sys_pll.vhd has the my_reset port because I need it for the equation in my process. I have a feeling though that that is not right.

I generated the IP, but I never got any code from it. I was unaware of that ability to take the template code. I learned about the IP from the youtube video and added it into the project as shown but did not know that I could take code from it that way. I thought it was a library that existed to help the compiler. I did not know what the top-level code was as I have no basis to go off of for the IP. So, the IP creates u0 and I need to make u1 for the sys_pll. Ok, I can do that. I copied the code the IP generated and I have:

u0 : component RRIP
port map (
ninit_done => CONNECTED_TO_ninit_done -- ninit_done.ninit_done
);

The CONNECTED_TO_ninit_done is not defined and is causing an error. This is not a signal, so how do I define this?

sys_clk and rst_in are variables I saw in the RRIP video, so I thought that they were needed. Perhaps I already have things defined and am creating redundant symbols. I would not put that past me. Locked is bidirectional as I saw it equaling itself i.e. locked => locked. I took it as this is a bidirectional pin.

With ninit_done being an output pin, I was under the impression that I would need an input pin for it as well to give data to something. If I cannot connect it to an input port, then I need an IF statement to say that it has changed? Or is there something else I can do?

The sys_rst is the flag saying that the system has reset that I saw on the video. Once I got my code running, I was going to use that as the checker to make sure the system reset. I thought that that was the point of it. I understand what the RRIP is supposed to do, but my ability to code it is far from perfect.

In the video they had the line locked => locked, so I thought that that was what I needed to do. It did not make sense to me either, but I trusted the video as it was from Intel. They should know their FPGA code is what I figured.

clockdiv is used for the main portion (sig.vhd) of the code to create a 25 MHz clock for the logic. The code will run on a frequency of 25 MHz.

I think I am slowly getting this as it is starting to make more sense now.

I did do the training, but it appears as though I need to go back through it. Oh boy. I am attaching the errors (meaningful errors) I am getting now and the code I have.

Thank you for your patience. I am trying my best to get this.

Drew

Hello,

Yes, I am aware. I just wanted to start off with something simple as a design to test the waters if you will. I plan on making much more complex designs later. I do not plan on buying a dev kit and I have seen 2 as PCIe slot card dev kits. I am planning on making my own FPGA board. I need the Agilex 7 M-series as it has DDR5 and PCIe Gen 5 capabilities. I need to use the modern standards so I can get more qualifications on my résumé. I have a majority of the parts I want for the board already in my PCB schematic, I am just missing the brains. I cannot find a model of the FPGA. I want to use Quartus 1st to make sure that I at least know what I will need to do when I make the board.

Thank you though for making sure I was aware of what I was doing,

Drew

Hi Drew,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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Have a great day!

Best regards,

Nurina W.

I do not know what should be a signal, a port, or something else. I am attaching my new code and errors. The Reset Release code is lines 13-27. I hope this looks better. I have tried to follow the tutorial for the Reset Release IP I found through Intel,