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MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Reset Release IP VHDL code not working

Hello, I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag. I am trying to create a Reset Release IP code snippet and cannot seem to figure out wh...
Hdl
  • Nurina's avatar
    Nurina
    2 years ago

    By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.

    The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.

    It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?

    Regards,

    Nurina

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Drew,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Feel free to open a new thread or login to ‘ https://supporttickets.intel.com ’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If any answer from the community or Intel Support are helpful, feel free to rank your support experience by rating 4/5 survey. Please let me know of any inconvenience so that I may improve your future service experience.

Have a great day!


Best regards,

Nurina W.


  • MATRIX7878's avatar
    MATRIX7878
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hello,

    Thank you for letting me know. I'm glad that this could be resolved as well. Now to figure out how to use the RRIP in the program.

    Drew