LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY toplevel IS
	PORT(L, R, H, my_reset, clk, clr : in std_logic;
			LC, LB, LA, RA, RB, RC : out std_logic);
END toplevel;

ARCHITECTURE behavior OF toplevel IS
	SIGNAL oclk, sys_rst : std_logic;
	
	COMPONENT sig IS
		PORT (L, R, H, clk : in std_logic;
			LC, LB, LA, RA, RB, RC : out std_logic);
	END COMPONENT;
	
	COMPONENT clockdiv IS
		PORT(iclk, clr : IN STD_LOGIC;
				oclk : OUT STD_LOGIC);
	END COMPONENT;
	
	COMPONENT RRIP IS
		port (
			ninit_done : out std_logic   -- ninit_done.ninit_done
		);
	END COMPONENT;
	
	COMPONENT sys_pll IS
		PORT (rst_in, clk, sys_clk : IN STD_LOGIC;
				refclk, outclk_0, rst : OUT STD_LOGIC;
				locked : INOUT std_logic);
	END COMPONENT;
	
	BEGIN
		a: sig PORT MAP (L, R, H, oclk, LC, LB, LA, RA, RB, RC);
		b: clockdiv PORT MAP (clk, clr, oclk);
		u0: RRIP PORT MAP (ninit_done => my_reset);
		u1: sys_pll PORT MAP (rst => rst_in, refclk => clk, locked => locked, outclk_0 => sys_clk);
		
END behavior;