Forum Discussion
Reset Release IP VHDL code not working
- 2 years ago
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Hello,
I decided to just dump all the RRIP I had and start from scratch as the program was giving me a headache. I found out how to see the .vhd file in the RRIP and saw that I had a conflicting naming convention for the files. That was probably some of the problems. I am still going through the online training of Intel, but I have not gotten to everything yet. I see the .vhd file associated with the RRIP has and see that it has an entity that deals with the ninit_done port. I have re-written the reset release file with this new file in mind and the links you all have sent me. I thought I could get the code right, but I still am not getting it. I do not know why this is not clicking with me. I also see that I had somehow mixed up a port. Locked equals to locked, not the out clock. I do not know why I saw that. The code looks much cleaner now, but it is still riddled with errors. I should get this by now, but I am not. The code without the RRIP compiles without error but gets a severe warning of no RRIP in the program. At this point, I am hoping someone has an actual file for RRIP.
Thank you,
Drew