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Occasional ContributorReset Release IP VHDL code not working
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Occasional ContributorHello,
Yes, I am aware. I just wanted to start off with something simple as a design to test the waters if you will. I plan on making much more complex designs later. I do not plan on buying a dev kit and I have seen 2 as PCIe slot card dev kits. I am planning on making my own FPGA board. I need the Agilex 7 M-series as it has DDR5 and PCIe Gen 5 capabilities. I need to use the modern standards so I can get more qualifications on my résumé. I have a majority of the parts I want for the board already in my PCB schematic, I am just missing the brains. I cannot find a model of the FPGA. I want to use Quartus 1st to make sure that I at least know what I will need to do when I make the board.
Thank you though for making sure I was aware of what I was doing,
Drew
