Forum Discussion
Occasional ContributorReset Release IP VHDL code not working
By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.
The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.
It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?
Regards,
Nurina
Super ContributorLots happening here.
When you generate IP, it creates a number of files. You just don't need to interact with them usually. The generated code is placed in folders in your project directory (may be the instance name you gave to the IP or in an "ip" directory). It looks like you took the top-level file generated by the PLL IP and edited it (adding my_reset) which you should not do.
The template includes "CONNECTED_TO_..." to indicate where you need to edit it to replace it with the appropriate connection in your design. That's why it's just a template and not the final code you should be using.
ninit_done is an output signal of the IP, not an actual hardware output pin of the device. As such, you could certainly connect it to an output pin of the device to bring the signal out of the FPGA or connect it to the input of some other logic (like a reset input for example). This does not mean you can connect it to an actual hardware input pin of the device. As I stated previously, this makes no sense.
And as I suspected, clkdiv is not required. It's not clear if you need one or two clock domains, but you could just use the PLL to create the divided clock instead.
Occasional ContributorHello,
I did not use the PLL IP. The only IP I have is the Reset Release IP. Is that what you are calling the sys_pll? I did not know that that was to come from an IP. I thought that that was its own code chunk.
Can the template space be replaced with a signal? It would then need to change the direction of the => to <= if I am not mistaken. I do not think that making it ninit_done => ninit_done makes sense, so I need to create a new port for it. Is that right?
Ok, I think that the label is defined as a PORT and not a SIGNAL, so I might have misunderstood what it was trying to become. Ah, I see what you are saying. ninit_done is a software signal that talks within the software, it is not a hardware signal that I can connect to an LED. I can connect it to another software pin that can trigger a hardware function to turn on an LED if I desire, but I cannot use the signal directly. I think that was a big part of the problem I was having with understanding.
clkdiv is needed at least for the LED and switch control of the main program. That was the clock I had before I knew that I had to have a Reset Release. It would probably be best to have two clock domains, one for the reset and one for the main program.
Thank you and hopefully Nurina, has finished with my .qar soon,
Drew
