LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY sig IS
	PORT(L, R, H, clk : in std_logic;
			LC, LB, LA, RA, RB, RC : out std_logic);
END sig;

ARCHITECTURE behavior OF sig IS
	TYPE statet IS (s0, s1, s2, s3, s4, s5, s6, s7);
	SIGNAL currentState, nextState : statet;
	
	PROCESS (currentState, L, R, H)
		VARIABLE INPUTS : std_logic_vector (2 downto 0);
		BEGIN
			INPUTS := L&R&H;
			CASE currentState IS
				WHEN s0 => IF (INPUTS = "000") THEN
					nextState <= s0;
				ELSIF (INPUTS = "100") THEN
					nextState <= s1;
				ELSIF (INPUTS = "010") THEN
					nextState <= s4;
				ELSE
					nextState <= s7;
				END IF;
			
				WHEN s1 => IF (INPUTS(0) = '1') THEN
					nextState <= s7;
				ELSIF (INPUTS = "100") THEN
					nextState <= s2;
				ELSE
					nextState <= s0;
				END IF;
				
				WHEN s2 => IF (INPUTS(0) = '1') THEN
					nextState <= s7;
				ELSIF (INPUTS = "100") THEN
					nextState <= s3;
				ELSE
					nextState <= s0;
				END IF;
				
				WHEN s3|s6 => IF (INPUTS(0) = '1') THEN
					nextState <= s7;
				ELSE
					nextState <= s0;
				END iF;
				
				WHEN s4 => IF (INPUTS(0) = '1') THEN
					nextState <= s7;
				ELSIF (INPUTS = "010") THEN
					nextState <= s5;
				ELSE
					nextState <= s0;
				END IF;
				
				WHEN s5 => IF (INPUTS(0) = '1') THEN
					nextState <= s7;
				ELSIF (INPUTS = "010") THEN
					nextState <= s6;
				ELSE
					nextState <= s0;
				END IF;
				
				WHEN s7 => nextState <= s0;
			END CASE;
	END PROCESS;
	
	PROCESS(clk)
	BEGIN
		IF rising_edge(clk) THEN
			currentState <= nextState;
		END IF;
	END PROCESS;
	
	PROCESS (currentState)
	BEGIN
		LC <= '0'; LB <= '0'; LA <= '0';
		RA <= '0'; RB <= '0'; RC <= '0';
		
			CASE currentState IS
				WHEN s0 => null;
				WHEN s1 => LA <= '1';
				WHEN s2 => LA <= '1'; LB <= '1';
				WHEN s3 => LA <= '1'; LB <= '1'; LC <= '1';
				WHEN s4 => RA <= '1';
				WHEN s5 => RA <= '1'; RB <= '1';
				WHEN s6 => RA <= '1'; RB <= '1'; RC <= '1';
				WHEN s7 => LA <= '1'; LB <= '1'; LC <= '1'; RA <= '1'; RB <= '1'; RC <= '1';
			END CASE;
	END PROCESS;
END behavior;