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MATRIX7878's avatar
MATRIX7878
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Reset Release IP VHDL code not working

Hello, I am trying to create a simple VHDL design test for an Agilex 7 m-series FPGA and have hit a snag. I am trying to create a Reset Release IP code snippet and cannot seem to figure out wh...
Hdl
  • Nurina's avatar
    Nurina
    2 years ago

    By the way, here is how your project netlist looks like in the RTL viewer. You should really check the connections and make sure if this is what you intended.

    The connections are easily changed through portmapping as I had helped you earlier. You may check out the VHDL trainings as it covers this.

    It seems like a very small project. What are you trying to do with this project? Are you just going to run simulations? Are you going to do hardware programming?

    Regards,

    Nurina

nadeem129aa's avatar
nadeem129aa
Icon for New Contributor rankNew Contributor
2 years ago

I do not know what should be a signal, a port, or something else. I am attaching my new code and errors. The Reset Release code is lines 13-27. I hope this looks better. I have tried to follow the tutorial for the Reset Release IP I found through Intel,

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Not seeing any attachments.