Qsys interconnect

Thank you for the response.

Yes, you understood correctly.

signal count : integer;

signal clk : std_logic;

signal s_reset_n : std_logic;

signal s_cs_enable : std_logic;

signal r_temp_count : std_logic_vector(31 downto 0);

process(clk)

begin

rising_edge(clk) then

if avs_scon_write_n = '0' then

case avs_scon_address is

when "000" =>

s_reset_n <= not avs_scon_writedata(0);

s_cs_enable <= avs_scon_writedata(1);

when others => null;

end case;

else

case avs_scon_address is

when "000" =>

r_temp_count <= std_logic_vector(to_unsigned(count,32));

when others => null;

end case;

end if;

end if;

end process;

avs_scon_readdata <= r_temp_count;

process(clk, s_reset_n)

begin

if s_reset_n = '0' then

count <= 0;

elsif rising_edge(clk) then

if (avs_s1_read = '1' or avs_s1_write = '1') and avm_m1_waitrequest_n = '1' and s_cs_enable = '1' then

count <= count + 1;

end if;

end if;

end process;

To read /write my component I am using another port. The signals are shown below.

-- Slave port connecting to the controller CPUCON

avs_scon_address : in std_logic_vector(2 downto 0);

avs_scon_readdata : out std_logic_vector(31 downto 0) := (others => 'X');

avs_scon_read_n : in std_logic;

avs_scon_writedata : in std_logic_vector(31 downto 0) := (others => 'X');

avs_scon_write_n : in std_logic;

avs_scon_waitrequest : out std_logic := 'X'

I don't need to count all the portion of my program. So before start to count, I reset and enable. Then I am doing some read, write onto data memory using IOWR_32DIRECT and IORD_32DIRECT (now for testing purpose) . Then I disable. Manual counting and the expected output are different. It counts more.

Thank you

Hi

Yes, Each component will have base address.

But when I examine address signal(avs_s1_address), it is byte address. So base address is invisible to us.?

Thank you

Hi

Thank you for the response.

Yeah, but I didn't mean that here.

In my component, when I count, I am using conditions. At that point if I check the incoming address is within data memory address range, I could narrow down the extra counts. The address signal (avs_s1_address) coming from NiosII has only byte address. So if we can get base address signal also, we could figure out if any other address range is counted.

Thanks

Hi

Thank you for the response.

Yeah, When I increase slowly, at some point it counts 95 extra, for the further increments the count error is multiples of 95.

Another thing is, when I increase clock frequency, the 1st point is going back. It means it could count more read/writes correctly. For less clock frequency the error comes early.

Thanks

Thank you for the reply.

Yeah I am using simplified version for debugging process.

As I said earlier, my program works correctly, even simple read/write or any other huge program.

Only problem is counting. We should prevent the counting during the clock cycle when the processor master is occupied with other slaves.

Thanks

Hi

Thank You.

Yes. I Signaltap both input(avs_s1_address) and output(avm_m1_address) signals. Both are same.

And also I collected memory access traces.

For example program (given bellow), I access same memory location. But in the memory access traces, there are some other memory addresses. As I said earlier, for certain number of read/write, in the middle there are continues 95 extra addresses, when I increase read/write, I could see another same set of extra addresses.

counter_RESET();

counter_ENABLE();

while(IORD_32DIRECT(BASE, 8) < 30000){

IOWR_32DIRECT(BASE, 8, IORD_32DIRECT(BASE, 8)+1);

}

counter_DISABLE();

Where these accesses are coming from? (Only NiosII data master is connected to Data memory.) And how can I prevent counting these accesses?

Thank You

Hi

Thank You.

I checked signals of data master port at Nios, counter's slave & master and on-chip-memory's slave port. Yep all are same. Those extra addresses are coming to on-chip-memory.

But still couldn't find what they are.

And another thing, for the same program (even without compiling again), these extra address sometimes come sometimes don't.

Thanks

Hi

Thank you for the response.

Actually my component is doing more using the data memory accesses at real time. For the debugging process I simplified as a simple counter.

I built a simple NiosII system with clk, id, timer, jtag uart, two onchipmemory (one for data memory and one for instruction memory), NiosII/f and counter. Accesses to data memory goes through counter.

NiosII/f settings: Reset vector memory: instruction memory offset:0

Exception vector memory: instruction memory offset:0x20

Instruction cache: 4Kbytes

Data Cache: None

Multiply/shift/Rotate Hardware: Auto selection

Include JTAG Debug

One more thing , now I could reduce those extra accesses from 95 to 9. When I create an application project using NiosII Software Build Tools, some settings I left as default. Now I changed these two to instruction memory : hal.linker.exception_stack_memory_region_name and hal.linker.interrupt_stack_memory_region_name. Now extra accesses are multiplies of 9.

Thanks