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ASubr1's avatar
ASubr1
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7 years ago

Qsys interconnect

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi, Thanks for sharing. As I look through the portion of code which do the counting, sorry as I am not able to spot any anomaly. To facilitate further debugging, I would recommend you to perform simple count ie one read or one write to see if your counter is able to capture it. Then slowly increase the number of read or write to see if can replicate issue. With simple count, this could help to narrow down unexpected read/write. Best regards, Chee Pin
ASubr1's avatar
ASubr1
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7 years ago

Hi

Thank you for the response.

Yeah, When I increase slowly, at some point it counts 95 extra, for the further increments the count error is multiples of 95.

Another thing is, when I increase clock frequency, the 1st point is going back. It means it could count more read/writes correctly. For less clock frequency the error comes early.

Thanks