New Contributor
Regular Contributor
New ContributorThank you for the response.
Yes, you understood correctly.
signal count : integer;
signal clk : std_logic;
signal s_reset_n : std_logic;
signal s_cs_enable : std_logic;
signal r_temp_count : std_logic_vector(31 downto 0);
process(clk)
begin
rising_edge(clk) then
if avs_scon_write_n = '0' then
case avs_scon_address is
when "000" =>
s_reset_n <= not avs_scon_writedata(0);
s_cs_enable <= avs_scon_writedata(1);
when others => null;
end case;
else
case avs_scon_address is
when "000" =>
r_temp_count <= std_logic_vector(to_unsigned(count,32));
when others => null;
end case;
end if;
end if;
end process;
avs_scon_readdata <= r_temp_count;
process(clk, s_reset_n)
begin
if s_reset_n = '0' then
count <= 0;
elsif rising_edge(clk) then
if (avs_s1_read = '1' or avs_s1_write = '1') and avm_m1_waitrequest_n = '1' and s_cs_enable = '1' then
count <= count + 1;
end if;
end if;
end process;
To read /write my component I am using another port. The signals are shown below.
-- Slave port connecting to the controller CPUCON
avs_scon_address : in std_logic_vector(2 downto 0);
avs_scon_readdata : out std_logic_vector(31 downto 0) := (others => 'X');
avs_scon_read_n : in std_logic;
avs_scon_writedata : in std_logic_vector(31 downto 0) := (others => 'X');
avs_scon_write_n : in std_logic;
avs_scon_waitrequest : out std_logic := 'X'
I don't need to count all the portion of my program. So before start to count, I reset and enable. Then I am doing some read, write onto data memory using IOWR_32DIRECT and IORD_32DIRECT (now for testing purpose) . Then I disable. Manual counting and the expected output are different. It counts more.
Thank you
