I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port of data memory connected here). So inside my component I just pass slave signals to master signals like shown below so that processor can access data memory as normal. (My program is running correctly) -- Pass the requests from CPU on to the memory avm_m1_address <= avs_s1_address; avs_s1_readdata <= avm_m1_readdata; avm_m1_read <= avs_s1_read; avm_m1_writedata <= avs_s1_writedata; avm_m1_write <= avs_s1_write; avs_s1_waitrequest_n <= avm_m1_waitrequest_n; avm_m1_burstbegin <= avs_s1_burstbegin; avm_m1_byteenable <= avs_s1_byteenable; avs_s1_rdata_valid <= avm_m1_rdata_valid; avm_m1_burstcount <= avs_s1_burstcount;And also inside my component I am counting number of data memory accesses made by the processor. But this counting seems like wrong. I am using this condition to count in every clock cycle: (clock is same for all)rising_edge(clk) then if (avs_s1_read = '1' or avs_s1_write = '1') and avm_m1_waitrequest_n = '1' thenIs this correct way to identify ONLY data memory access? Processor data master is also connected to other slave as well (slave of system id, timer, jtag uart, instruction memory). How Qsys identifies the correct slave port? Using Destination_ID? Is it accessible? or invisible?Next thing Qsys uses byte address. So we can’t restrict without knowing base address.Thanks

Hi, As I understand it, you have some inquiries related to the counting of data memory access by NIOs II using your custom component. If I understand it correctly, the avs_s1_read is the read signal and avs_s1_write is the write signal from NIOs II. By merely looking at the condition, there seems to be no anomaly. Would you mind to share further on the following: 1. Would you mind to share further on your counting code? The current code seems to show only the condition but not the counting portion? 2. Mind further elaborate on the counting wrong observation? Please let me know if there is any concern. Thank you. Best regards, Chee Pin

Hi, Regarding your inquiry on how Qsys identify the specific slave, as I understand it, in the Qsys system, each component or slave will have a specific base address. Master will use the base address to identify the target slave. Please let me know if there is any concern. Thank you. Best regards, Chee Pin

Thank you for the response.Yes, you understood correctly. signal count : integer; signal clk : std_logic; signal s_reset_n : std_logic; signal s_cs_enable : std_logic; signal r_temp_count : std_logic_vector(31 downto 0); process(clk) begin rising_edge(clk) then if avs_scon_write_n = '0' then case avs_scon_address is when "000" => s_reset_n <= not avs_scon_writedata(0); s_cs_enable <= avs_scon_writedata(1); when others => null; end case; else case avs_scon_address is when "000" => r_temp_count <= std_logic_vector(to_unsigned(count,32)); when others => null; end case; end if; end if; end process; avs_scon_readdata <= r_temp_count; process(clk, s_reset_n)begin if s_reset_n = '0' then count <= 0; elsif rising_edge(clk) then if (avs_s1_read = '1' or avs_s1_write = '1') and avm_m1_waitrequest_n = '1' and s_cs_enable = '1' then count <= count + 1; end if; end if;end process; To read /write my component I am using another port. The signals are shown below. -- Slave port connecting to the controller CPUCON avs_scon_address : in std_logic_vector(2 downto 0); avs_scon_readdata : out std_logic_vector(31 downto 0) := (others => 'X'); avs_scon_read_n : in std_logic; avs_scon_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); avs_scon_write_n : in std_logic; avs_scon_waitrequest : out std_logic := 'X'I don't need to count all the portion of my program. So before start to count, I reset and enable. Then I am doing some read, write onto data memory using IOWR_32DIRECT and IORD_32DIRECT (now for testing purpose) . Then I disable. Manual counting and the expected output are different. It counts more.Thank you

HiYes, Each component will have base address.But when I examine address signal(avs_s1_address), it is byte address. So base address is invisible to us.? Thank you

Hi, You will need to know the base address from your Qsys system so that you can access them through NIOs II. Generally for accessing certain offset of a module, we will need to multiple the offset by 4 ie $base_addr + $offset * 4

ASubr1

New Contributor

6 years ago

Qsys interconnect

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port of data memory connected here). So inside my component I just pass slave signals to master signals like shown below so that processor can access data memory as normal. (My program is running correctly)

-- Pass the requests from CPU on to the memory

avm_m1_address <= avs_s1_address;

avs_s1_readdata <= avm_m1_readdata;

avm_m1_read <= avs_s1_read;

avm_m1_writedata <= avs_s1_writedata;

avm_m1_write <= avs_s1_write;

avs_s1_waitrequest_n <= avm_m1_waitrequest_n;

avm_m1_burstbegin <= avs_s1_burstbegin;

avm_m1_byteenable <= avs_s1_byteenable;

avs_s1_rdata_valid <= avm_m1_rdata_valid;

avm_m1_burstcount <= avs_s1_burstcount;

And also inside my component I am counting number of data memory accesses made by the processor. But this counting seems like wrong. I am using this condition to count in every clock cycle: (clock is same for all)

rising_edge(clk) then

if (avs_s1_read = '1' or avs_s1_write = '1') and avm_m1_waitrequest_n = '1' then

Is this correct way to identify ONLY data memory access?

Processor data master is also connected to other slave as well (slave of system id, timer, jtag uart, instruction memory). How Qsys identifies the correct slave port? Using Destination_ID? Is it accessible? or invisible?

Next thing Qsys uses byte address. So we can’t restrict without knowing base address.

Thanks

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Qsys interconnect

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