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ASubr1's avatar
ASubr1
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7 years ago

Qsys interconnect

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port...
Ahmed_H_Intel1's avatar
Ahmed_H_Intel1
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6 years ago

Hi,

Did you check the interrupt configuration (please share with me these configurations) or use Vectored Interrupt controller VIC instead to see if the same issue exists?

Thanks

  • ASubr1's avatar
    ASubr1
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    With the EIC using VIC, still we get that unknown accesses but 9 comes to 7.

    Thanks