Forum Discussion
ASubr1
New Contributor
New ContributorQsys interconnect
I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port...
CheepinC_altera
Regular Contributor
Regular ContributorHi,
Thanks for your update. For your information, based on the current observation, I think you would need to further debug into your counting algorithm to see if can spot any anomaly.
I would like to suggest you to create a simple design or simplify your existing design by using on-chip memory. Then perform 100 writes to on-chip memory. You may write data 1 to 100 to the memory to ease debugging. You can read back the data to verify if data are written correctly to the memory. Signaltap the signals at the slave of your counting component, master of your counting component which connect to memory and the internal counters. Then perform a cross check among these signals and counter values to further narrow down the issue.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
ASubr1New Contributor
New ContributorThank you for the reply.
Yeah I am using simplified version for debugging process.
As I said earlier, my program works correctly, even simple read/write or any other huge program.
Only problem is counting. We should prevent the counting during the clock cycle when the processor master is occupied with other slaves.
Thanks
