Forum Discussion
New ContributorQsys interconnect
Frequent ContributorHi Arudchutha,
First of all, I see you can count the read/write via NIOS II by adding a PIO component from NIOS Qsys that goes up every write or read command happens, or to use the C-code in NIOS in counting the read/write executions.
One more thing, This might be a cash issue, i think you need to clear the On-Chip memory cash first to be sure that you see the correct count. I am not sure as I didn't see how you constructed your system, please correct me If I understood the issue wrongly.
In the new case you can mention my name while creation and I will be following with you this issue.
Regards,
New ContributorHi
Thank you for the response.
Actually my component is doing more using the data memory accesses at real time. For the debugging process I simplified as a simple counter.
I built a simple NiosII system with clk, id, timer, jtag uart, two onchipmemory (one for data memory and one for instruction memory), NiosII/f and counter. Accesses to data memory goes through counter.
NiosII/f settings: Reset vector memory: instruction memory offset:0
Exception vector memory: instruction memory offset:0x20
Instruction cache: 4Kbytes
Data Cache: None
Multiply/shift/Rotate Hardware: Auto selection
Include JTAG Debug
One more thing , now I could reduce those extra accesses from 95 to 9. When I create an application project using NiosII Software Build Tools, some settings I left as default. Now I changed these two to instruction memory : hal.linker.exception_stack_memory_region_name and hal.linker.interrupt_stack_memory_region_name. Now extra accesses are multiplies of 9.
Thanks
- ASubr1
Hi
I could find that those unknown data memory accesses are because of Interval Timer interrupt. But I still wonder what hardware interrupt does with data memory even after changing interrupt_stack_memory_region to instruction memory. Anyway I could eliminate those extra accesses by preventing timer interrupt request for a certain portion of my program where I am taking data memory accesses. But disabling hardware interrupts is not a good solution right? What are that read/write to data memory during timer interrupt?
Thanks
