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ASubr1's avatar
ASubr1
Icon for New Contributor rankNew Contributor
7 years ago

Qsys interconnect

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Thanks for your update. As I understand it from your latest observation, it seems like you are observing NIOs II intermittently feed additional address to on chip memory. For your information, I have duplicated a new case 04276053 to seek further assistance from NIOs II SMEs. I have informed respective team to expedite the case routing.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin