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ASubr1's avatar
ASubr1
Icon for New Contributor rankNew Contributor
7 years ago

Qsys interconnect

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Thanks for your update. If I understanding it correctly, in your current simple test design, you have NIOs II -> Counter -> On-chip Memory. Just wonder if you have had a chance to signaltap the following during a write only process:

1. write from NIOs

2. write the On-chip Memory

You can then cross check if the write activities are tally. With this method, you could isolate the addressing from the debugging.

Please let me know if there is any concern. Thank you.

Best regards,

Chee Pin

  • ASubr1's avatar
    ASubr1
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hi

    Thank You.

    I checked signals of data master port at Nios, counter's slave & master and on-chip-memory's slave port. Yep all are same. Those extra addresses are coming to on-chip-memory.

    But still couldn't find what they are.

    And another thing, for the same program (even without compiling again), these extra address sometimes come sometimes don't.

    Thanks