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ASubr1's avatar
ASubr1
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6 years ago

Qsys interconnect

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, Thanks for your update. Just wonder if you have had a chance to try signaltaping the signals at the interfaces of involved component to further narrow down the issue? thank you.
  • ASubr1's avatar
    ASubr1
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi

    Thank You.

    Yes. I Signaltap both input(avs_s1_address) and output(avm_m1_address) signals. Both are same.

    And also I collected memory access traces.

    For example program (given bellow), I access same memory location. But in the memory access traces, there are some other memory addresses. As I said earlier, for certain number of read/write, in the middle there are continues 95 extra addresses, when I increase read/write, I could see another same set of extra addresses.

    counter_RESET();

    counter_ENABLE();

    while(IORD_32DIRECT(BASE, 8) < 30000){

    IOWR_32DIRECT(BASE, 8, IORD_32DIRECT(BASE, 8)+1);

    }

    counter_DISABLE();

    Where these accesses are coming from? (Only NiosII data master is connected to Data memory.) And how can I prevent counting these accesses?

    Thank You