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ASubr1's avatar
ASubr1
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7 years ago

Qsys interconnect

I have a Nios II processor system with my own Qsys component which to monitor data memory access. The component has one slave (s1) (Nios data master is connected here) and one master (m1) (slave port...
CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
7 years ago
Hi, Regarding your inquiry on how Qsys identify the specific slave, as I understand it, in the Qsys system, each component or slave will have a specific base address. Master will use the base address to identify the target slave. Please let me know if there is any concern. Thank you. Best regards, Chee Pin
ASubr1's avatar
ASubr1
Icon for New Contributor rankNew Contributor
7 years ago

Hi

Yes, Each component will have base address.

But when I examine address signal(avs_s1_address), it is byte address. So base address is invisible to us.?

Thank you