Forum Discussion

JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cyclone 10GX PCIe Hard IP bring up

Hi,

My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager). I've programmed it with a basic FPGA code based on example project i've used on the Cyclone 10 dev board.

Any tips on how i can go about debugging this? I can see refclk activity and perst at logic high. But the core clock out of the PCIe hard IP is not toggling. Stuck at logic low.

Thanks.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    4 years ago

    From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



27 Replies

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    What is the target speed of PCIe, is this Gen2x4?


    What is the status of the following signals?

    1. ltssmstate
    2. current_spped
    3. lane_act


    Regards -SK


      • JBayl's avatar
        JBayl
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Hi,

        I'm having issues using Signal Tap. In stand alone set up using custom test jig providing 3.3V power to the PCIe board, FPGA programming works, that's using either Programmer or Signal Tap. I can also program the quad serial config device (Micron's MT25QU256) through Programmer.

        But Signal Tap reports that I still need to Program the device to continue even after successful SOF programming.

        When the PCIe board is inside a PC, Signal Tap can't program the FPGA. It reports that CONF_DONE pin failed to go high on device 1. There's only 1 FPGA device on the chain.

        Its looking like a hardware issue because 2 boards have the same behaviour, but the fact that Programmer works and Signal Tap doesn't confuses me a bit on where to look. Any advice?

        Just in case, the FPGA is a 10CX085YU484I5G. Saw some posts pointing to Stratix device issues.

        Thanks!

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Could you please ensure you have saved the signal tap properly, and then enable it from the Assignments (Quartus Menu)-> Settings -> Signal Tap Logic Analyser -> Enable Signal Tap logic analyzer (with the correct file name) before compiling the design?


    • JBayl's avatar
      JBayl
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi SK,

      Signal Tap is now running OK. I created the STP file based on Section 15.4 on ug_01145_avmm (2019.12.20) Intel Arria/Cyclone MM Interface for PCIe User Guide. Most of the automatically added signals are red, so I searched for the nodes and re-added a few key signals.

      I don't see any activity on the ltssmstate, currentspeed, or lane_act. PERST also appears to be stuck HIGH. I use PERST as a trigger when it transitions to ZERO, or when it has a zero value on Signal Tap.

      Here are my steps:

      1. power on PC with PCIe card inserted that's hooked up on a byteblaster on a different machine.

      2. program the FPGA using Programmer (SOF).

      3. Run Analysis on Signal Tap.

      4. Initiate a Restart on the PC (through Windows, not Reset button) )with the PCIe card. I'm assuming a reenumeration happens here. I can see PERST toggling when I do this PC restart but Signal Tap isn't capturing it. I've inserted a counter, and Signal Tap triggers on it when I set the trigger to a counter value.

      cause core_clk_out_clk looks stuck. What would cause this if refclk is toggling and the system isn't in reset?

      Power up sequence looks OK. 3.3V first, then 0.9/0.95, then 1.8, then 3V. All within 100ms with the main 3.3V input from PCIe kicking it off.

      Thanks!

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Can you attach a simplified PCIe design that can replicate the problem here? I would like to do a sanity check on your design. Thanks.


      • JBayl's avatar
        JBayl
        Icon for Occasional Contributor rankOccasional Contributor
        4 years ago

        Hi,

        I've powered up 3 boards and all aren't getting recognized. Main issue I see is that the core_clk_out_clk output of the HIP isn't toggling. I tied it up to a counter to a test point and no activity. PERST is high, which is OK, deasserted state. Refclk is toggling OK.

        I think that may be the reason why I can't see the ltssmstate and other debug signals not toggling. No clock. Any advice where I should look?

        Power up sequence looks OK. All sources OK within 100ms.

        Thanks!

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Is the clk0 in your design a free-running clock? What is the frequency? Does the PCIe ref clock is from the RP (via gold finger), or it is a local clock?


    • JBayl's avatar
      JBayl
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      clk0 @ pin U1 is a 27Mhz free running clock. This clock is meant for our custom logic.

      PCIe refclk is from PC through the gold fingers. I have it at 100Mhz.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,


    Could you please add the following in the QSF file, and then recompile the design and capture the signal tap again?

    set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1


    Regards -SK


    • JBayl's avatar
      JBayl
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Attached pdf shows what i'm seeing on signal tap.

      Added that line you suggested on qsf, recompiled, programmed the MT25QU256, then power cycle.

      Run acquire on SignalTap. I used clk0 (27Mhz) free running clock as SignalTap clock source.

      Rechecked pin connection guidelines and all looks OK. It all appears to be pointing to PLL not locking...

    • JBayl's avatar
      JBayl
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Hi SK,

      clkusr is sourced from a XG-1000CA 100.0000M-EBL3 powered @1.8V (group2 power supply) with output frequency of 100Mhz hooked up on pin AA6 (10CXYU484). It looks clean and OK at power up on a freshly powered board.

      But not on a board that's been powered up too long. Can feel the board hot with 1.8V getting periodically shutdown by regulator.

      I'm using EN6340QI for 0.9 and VCCT/R_GXB. EN5319QI for 3V and 1.8V.

      Thanks!

      • SengKok_L_Intel's avatar
        SengKok_L_Intel
        Icon for Regular Contributor rankRegular Contributor
        4 years ago

        Hi,

        I can't see anything that can cause the PCIe fPLL fall to lock from the Quartus project.

        To further understand the problem, I have added some additional signals, could you please help to capture the signal tap by using the attached SOF file?

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    The coreclkou and the fpll counter are still zero. Does the clk0 (27Mhz) change to 54Mhz is expected?


    • JBayl's avatar
      JBayl
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Hi SK,

      That's weird, clk0 at pin U1 is fixed at 27Mhz from an output of CDCEL913PWR. This CDCEL913PWR isn't programmed and just passes through its input clock of 27Mhz. Scope shows constant 27Mhz output.

      I've done a couple of SignalTap runs and the values are changing for clk0_freq. Most of the time in multiples, like 27Mhz, 54Mhz, and 108Mhz. Sometimes odd values like 81Mhz. That's with top_cal.sof.

      Thanks!

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



    • JBayl's avatar
      JBayl
      Icon for Occasional Contributor rankOccasional Contributor
      4 years ago

      Thanks SK! Your responses helped a lot in narrowing down the issue.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


  • GRose12's avatar
    GRose12
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi,

    I have a new design using the Cyclone 10GX 10CX105YF672 part. I am trying to get my PCIe Hard IP running. I am concerned that I may have connected to the wrong transceiver pins. I am creating a Gen2 1X PCIe interface. I connected the PCIE-TX to U26/U25 pins and I connect the PCIE-RX T23/T24. I connected the PCIE_REFCLK to U22/U21. I am not able to see the clock in signal tap coming out the coreclkout_hip signal at all. I'm concerned that I should have used a different clock pair of pins (pins N22/N21).

    If I am right that I am on the wrong clock pins, is there a way to share clock pins within the PCIe Hard IP Tool?

    Thanks