Occasional ContributorFrom the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.
Regular ContributorHi,
Could you please ensure you have saved the signal tap properly, and then enable it from the Assignments (Quartus Menu)-> Settings -> Signal Tap Logic Analyser -> Enable Signal Tap logic analyzer (with the correct file name) before compiling the design?
Occasional ContributorHi SK,
Signal Tap is now running OK. I created the STP file based on Section 15.4 on ug_01145_avmm (2019.12.20) Intel Arria/Cyclone MM Interface for PCIe User Guide. Most of the automatically added signals are red, so I searched for the nodes and re-added a few key signals.
I don't see any activity on the ltssmstate, currentspeed, or lane_act. PERST also appears to be stuck HIGH. I use PERST as a trigger when it transitions to ZERO, or when it has a zero value on Signal Tap.
Here are my steps:
1. power on PC with PCIe card inserted that's hooked up on a byteblaster on a different machine.
2. program the FPGA using Programmer (SOF).
3. Run Analysis on Signal Tap.
4. Initiate a Restart on the PC (through Windows, not Reset button) )with the PCIe card. I'm assuming a reenumeration happens here. I can see PERST toggling when I do this PC restart but Signal Tap isn't capturing it. I've inserted a counter, and Signal Tap triggers on it when I set the trigger to a counter value.
cause core_clk_out_clk looks stuck. What would cause this if refclk is toggling and the system isn't in reset?
Power up sequence looks OK. 3.3V first, then 0.9/0.95, then 1.8, then 3V. All within 100ms with the main 3.3V input from PCIe kicking it off.
Thanks!
