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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cyclone 10GX PCIe Hard IP bring up

Hi, My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager). I've programmed it with a basic FPGA code based on example pr...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Can you attach a simplified PCIe design that can replicate the problem here? I would like to do a sanity check on your design. Thanks.


  • JBayl's avatar
    JBayl
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    I've powered up 3 boards and all aren't getting recognized. Main issue I see is that the core_clk_out_clk output of the HIP isn't toggling. I tied it up to a counter to a test point and no activity. PERST is high, which is OK, deasserted state. Refclk is toggling OK.

    I think that may be the reason why I can't see the ltssmstate and other debug signals not toggling. No clock. Any advice where I should look?

    Power up sequence looks OK. All sources OK within 100ms.

    Thanks!

    • SengKok_L_Intel's avatar
      SengKok_L_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi,

      Could you please use the attached SOF file and capture the signal tap? I would like to see if I can spot anything.

      • JBayl's avatar
        JBayl
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        It's getting triggered right away. See attached pdf with screen shots.

        Result is the same with opening the stp file and programmer independently or adding the STP on a project, compile, and then Signal Tap programs the FPGA with the SOF you've provided. freq_out is the only signal changing.

        Noticed that the serdes_pll_locked and pll_locked_fpll isn't high. I assume these are high asserted. May explain why i'm not seeing coreclkout. But what's causing it...???