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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cyclone 10GX PCIe Hard IP bring up

Hi, My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager). I've programmed it with a basic FPGA code based on example pr...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

The coreclkou and the fpll counter are still zero. Does the clk0 (27Mhz) change to 54Mhz is expected?


  • JBayl's avatar
    JBayl
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi SK,

    That's weird, clk0 at pin U1 is fixed at 27Mhz from an output of CDCEL913PWR. This CDCEL913PWR isn't programmed and just passes through its input clock of 27Mhz. Scope shows constant 27Mhz output.

    I've done a couple of SignalTap runs and the values are changing for clk0_freq. Most of the time in multiples, like 27Mhz, 54Mhz, and 108Mhz. Sometimes odd values like 81Mhz. That's with top_cal.sof.

    Thanks!