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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cyclone 10GX PCIe Hard IP bring up

Hi, My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager). I've programmed it with a basic FPGA code based on example pr...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Could you please add the following in the QSF file, and then recompile the design and capture the signal tap again?

set_global_assignment -name VERILOG_MACRO "ALTERA_XCVR_A10_DISABLE_RESET_CONNECTED_TO_CAL_BUSY=1


Regards -SK


JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Attached pdf shows what i'm seeing on signal tap.

Added that line you suggested on qsf, recompiled, programmed the MT25QU256, then power cycle.

Run acquire on SignalTap. I used clk0 (27Mhz) free running clock as SignalTap clock source.

Rechecked pin connection guidelines and all looks OK. It all appears to be pointing to PLL not locking...