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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cyclone 10GX PCIe Hard IP bring up

Hi, My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager). I've programmed it with a basic FPGA code based on example pr...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    4 years ago

    From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Is the clk0 in your design a free-running clock? What is the frequency? Does the PCIe ref clock is from the RP (via gold finger), or it is a local clock?


  • JBayl's avatar
    JBayl
    Icon for Occasional Contributor rankOccasional Contributor
    4 years ago

    clk0 @ pin U1 is a 27Mhz free running clock. This clock is meant for our custom logic.

    PCIe refclk is from PC through the gold fingers. I have it at 100Mhz.