Forum Discussion
Occasional ContributorCyclone 10GX PCIe Hard IP bring up
From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.
Regular ContributorHi,
Could you please also check the CLKUSR, to ensure it is properly connected with the correct clock frequency and the clock is stable at the start of the device?
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf
Regards -SK
JBaylHi SK,
clkusr is sourced from a XG-1000CA 100.0000M-EBL3 powered @1.8V (group2 power supply) with output frequency of 100Mhz hooked up on pin AA6 (10CXYU484). It looks clean and OK at power up on a freshly powered board.
But not on a board that's been powered up too long. Can feel the board hot with 1.8V getting periodically shutdown by regulator.
I'm using EN6340QI for 0.9 and VCCT/R_GXB. EN5319QI for 3V and 1.8V.
Thanks!
- SengKok_L_Intel
Hi,
I can't see anything that can cause the PCIe fPLL fall to lock from the Quartus project.
To further understand the problem, I have added some additional signals, could you please help to capture the signal tap by using the attached SOF file?
- JBayl
Hi SK,
See attached pdf.
Configured the FPGA. Acquired and got the signals as in the pdf.
Restarted the PC and tried acquisition multiple times and same output waveform with freq_out the only signal changing.
The power on sequence of the regulators looks OK and within 100ms. What else could I still be missing...
Thanks!
