Forum Discussion
Occasional ContributorCyclone 10GX PCIe Hard IP bring up
From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.
Regular ContributorHi,
What is the target speed of PCIe, is this Gen2x4?
What is the status of the following signals?
- ltssmstate
- current_spped
- lane_act
Regards -SK
JBaylHi SK,
Its set to Gen2x1 64 bit, 125Mhz.
I found references to the signals you mentioned in Section 15.2 from here:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_avmm.pdf
I'll update you once I've managed to get Signal Tap setup.
Thanks!
r/jb
- JBayl
Hi,
I'm having issues using Signal Tap. In stand alone set up using custom test jig providing 3.3V power to the PCIe board, FPGA programming works, that's using either Programmer or Signal Tap. I can also program the quad serial config device (Micron's MT25QU256) through Programmer.
But Signal Tap reports that I still need to Program the device to continue even after successful SOF programming.
When the PCIe board is inside a PC, Signal Tap can't program the FPGA. It reports that CONF_DONE pin failed to go high on device 1. There's only 1 FPGA device on the chain.
Its looking like a hardware issue because 2 boards have the same behaviour, but the fact that Programmer works and Signal Tap doesn't confuses me a bit on where to look. Any advice?
Just in case, the FPGA is a 10CX085YU484I5G. Saw some posts pointing to Stratix device issues.
Thanks!
