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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cyclone 10GX PCIe Hard IP bring up

Hi, My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager). I've programmed it with a basic FPGA code based on example pr...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi SK,

clkusr is sourced from a XG-1000CA 100.0000M-EBL3 powered @1.8V (group2 power supply) with output frequency of 100Mhz hooked up on pin AA6 (10CXYU484). It looks clean and OK at power up on a freshly powered board.

But not on a board that's been powered up too long. Can feel the board hot with 1.8V getting periodically shutdown by regulator.

I'm using EN6340QI for 0.9 and VCCT/R_GXB. EN5319QI for 3V and 1.8V.

Thanks!

SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

I can't see anything that can cause the PCIe fPLL fall to lock from the Quartus project.

To further understand the problem, I have added some additional signals, could you please help to capture the signal tap by using the attached SOF file?

  • JBayl's avatar
    JBayl
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi SK,

    See attached pdf.

    Configured the FPGA. Acquired and got the signals as in the pdf.

    Restarted the PC and tried acquisition multiple times and same output waveform with freq_out the only signal changing.

    The power on sequence of the regulators looks OK and within 100ms. What else could I still be missing...

    Thanks!

    • SengKok_L_Intel's avatar
      SengKok_L_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi

      From the signal tap, even if using an fPLL with core mode, it is unable to lock. I have added an IO PLL into the design and use PCIe refclk as the reference clock. Please capture the signal tap by using the attached two sof files.

      • JBayl's avatar
        JBayl
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Hi SK,

        Found a hardware fault wherein the translator chip for PERST was populated wrong (rotated 180 degrees). Fixed it on 1 board and tried the sof and stp files you've sent. Waveforms attached.

        I can see serdes_pll_locked and io pll locked asserted on both sofs. Board is still not detected by windows.

        Thanks!