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JBayl's avatar
JBayl
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Cyclone 10GX PCIe Hard IP bring up

Hi, My custom PCIe board with Cyclone 10GX is not getting recognized by my PC (no unknown device getting displayed on Device Manager). I've programmed it with a basic FPGA code based on example pr...
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    5 years ago

    From the signal tap, it can check the clk0 frequency, and it is based on the 100Mhz PCIe reference clock. It sounds like either the clk0 itself or the 100Mhz PCIe reference clock is not stable.



GRose12's avatar
GRose12
Icon for New Contributor rankNew Contributor
3 years ago

Hi,

I have a new design using the Cyclone 10GX 10CX105YF672 part. I am trying to get my PCIe Hard IP running. I am concerned that I may have connected to the wrong transceiver pins. I am creating a Gen2 1X PCIe interface. I connected the PCIE-TX to U26/U25 pins and I connect the PCIE-RX T23/T24. I connected the PCIE_REFCLK to U22/U21. I am not able to see the clock in signal tap coming out the coreclkout_hip signal at all. I'm concerned that I should have used a different clock pair of pins (pins N22/N21).

If I am right that I am on the wrong clock pins, is there a way to share clock pins within the PCIe Hard IP Tool?

Thanks