Forum Discussion

ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

1/2.5/5/10G Multi-rate Ethernet PHY simulation cannot reach rx_block_lock

The simulation of the example design, provided by the "Low Latency Ethernet 10G MAC" IP, is running fine.

However, when simulating my design, the PHY can not acheive rx_block_lock.

The waveform shows that, for a loopback pair, the xgmii_tx_data of the TX side is 200_009c_0200_009c, while xgmii_rx_data of the RX side is 100_009c_0100_009c. It seems one 1-bit is missing and hence rx_block_lock is never asserted. The whole simulation went timeout.

From the log there is one warning:

Warning : At time = 3088266ps

tb_top.DUT.i_eth1g10g_i0.CHANNEL_GEN[6].u_channel.phy.alt_mge_phy_0.alt_mge_xcvr_native.g_xcvr_native_insts[0].ct2_xcvr_native_inst.inst_ct2_xcvr_channel_multi.gen_rev.ct2_xcvr_channel_inst.gen_ct1_hssi_aibcr_rx.inst_ct1_hssi_aibcr_rx.ct1_hssi_aibcr_rx_encrypted_inst.PROTECTED

Warning : The Nand Delay chain step size is larger than 80 ps, measured step size = 40ps and/or 1050ps

This warning looks fishy and it did not show up when simulating the example design.

Please help. Many thanks.

14 Replies

  • ZWang142's avatar
    ZWang142
    Icon for New Contributor rankNew Contributor
    5 years ago

    More info: in my waveform,

    rx_cdr_refclk_1 is 322.265625 MHz, as specified by the Reference clock frequency for 10 GbE (MHz) parameter.

    However,

    rx_pma_clkout is only 78 MHz (it should be 156.25 MHz according to the spec).

    • ZWang142's avatar
      ZWang142
      Icon for New Contributor rankNew Contributor
      5 years ago

      BTW, the warning has been solved. I copied tb_top.sv from the example design, where the refclk_10g is 644 Mhz, while in my design, it should be 322 Mhz. After changing refclk_10g to 322 Mhz, the warning is gone. But rx_pma_clkout is 78 Mhz...

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,

    The Multirate PHY IP has parameter setting for "Reference clock frequency for

    10 GbE (MHz)" where user needs to specify whether you prefer PLL refclk input is 644MHz or 322MHZ

    Whatever clock frequency that you provided in test bench design needs to match with the setting in Multirate PHY IP.

    Can you double check your Multirate PHY IP setting again ?

    Thanks.

    Regards,

    dlim

  • ZWang142's avatar
    ZWang142
    Icon for New Contributor rankNew Contributor
    5 years ago

    Yes, I double checked and it is 322 MHz in the IP settings.

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,

    Thanks for the clarification.

    rx_pma_clkout is derived from rx_cdr_refclk_1. If you have provided correct clock frequency in test bench file then by right rx_pma_clkout should be 156.25MHz.

    • I need to understand your design better and try to duplicate issue from my side.

    Can you share with me more info as below ?

    1. Which FPGA product that you are using ? Is it Stratix 10 ? Can you share with me your FPGA part number ?
    2. Which Quartus version that you are using ? Have you tried with latest Quartus version like Quartus Pro v20.1 ?
    3. Which simulator tool and what version that you are using ? Make sure you are using the corresponding simulator tool that pair with its Quartus version
    4. Do you had a chance to try out other simulator tool to see of the issue still persist ?
    5. Lastly, can you share with me your Multirate-PHY IP setting screenshot ?

    Thanks.

    Regards,

    dlim

    • ZWang142's avatar
      ZWang142
      Icon for New Contributor rankNew Contributor
      5 years ago

      0. My rx_cdr_refclk_1 is 322.265 Mhz.

      1- Stratix 10, 1SM16BEU2F55E2VG

      2- Quartus Pro v20.1

      3- VCS 2017

      4- I tried Modelsim 10.6 on Windows but it failed to handle long file names. The testbench files provided by the example design have very long file names.

      5- Please see the attached

    • ZWang142's avatar
      ZWang142
      Icon for New Contributor rankNew Contributor
      5 years ago

      In the example design, I changed the refclk to 322 MHz:

      • Changed IP settings for the PHY and generated HDL for both syn and sim
      • Changed IP settings for the 10g PLL and genreated HDL
      • Changed refclk_10g in tb_top to 322 MHz
      • Generated simulation scripts using Quartus
      • Changed other simulation scripts so VCS can compile

      Now, in the example design, rx_pma_clkout becomes 78 MHz and it cannot achive rx_block_lock.

      Would you please try 322 MHz for the "alt_em10g32_0_EXAMPLE_DESIGN/LL10G_1G_2_5G_10G" example design?

      Thanks.

      ​

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,

    Thanks. This is great info.

    let me try to duplicate this issue on the example design from my side.

    Regards,

    dlim

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    I am able to duplicate the 322MHz example design sim run failure (rx_block_lock) stay low issue even in modelsim. While sim run with 644MHz setting is fine.

    I am now consulting internally within Intel to figure out is this a bug or something that we miss out when using 322MHz setting.

    Will keep you posted on status update

    Thanks.

    Regards,

    dlim

    • ZWang142's avatar
      ZWang142
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi @DeshiL_Intel​ ,

      There is a core_pll in models/tb_top.sv that also needs to be changed, as it uses refclk_10g as well.

      After modifying this pll, the example design is able to run with refclk_10g at 322 MHz.

      Now I'm checking what's wrong with my design...

      Thanks.

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    Interesting.

    refclk_10g is used in 3 IP. I made below design changes but Modelsim run still failed.

    • Can you let me know what's the exact changes that you made ?

    Below is the modification steps

    • Generate Eth 10G MAC + MultiratePHY with default refclk 644MHz
    • Then change refclk from 644MHz to 322MHz for below 3 IP and regenerate the IP
      • Multirate PHY, ATX_PLL 10G, core_fPLL
    • Modify test bench (tb_top.sv) refclk_10g from 644MHz to 322MHz
    • Modify certain IP design files name as the IP has been regenerated (modelsim_files.tcl) in \simulation\ed_sim\setup_scripts\common

    Thanks.

    Regards,

    dlim

    • ZWang142's avatar
      ZWang142
      Icon for New Contributor rankNew Contributor
      5 years ago

      Forgot to mention: you have to copy the mif files from the newly generated PHY, to the rtl/reconfig folder of the example design...

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    HI,

    Thanks. I copied over the newly generated mif file to rtl/reconfig folder. Now, I can see that rx_block_lock asserted high.

    Hopefully you can find out what's wrong with your design as well. All the best to your project development.

    Regards,

    dlim

  • Deshi_Intel's avatar
    Deshi_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    For now, I am setting this case to closure.

    Thanks.

    Regards,

    dlim