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ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

1/2.5/5/10G Multi-rate Ethernet PHY simulation cannot reach rx_block_lock

The simulation of the example design, provided by the "Low Latency Ethernet 10G MAC" IP, is running fine. However, when simulating my design, the PHY can not acheive rx_block_lock. The waveform sho...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

HI,

The Multirate PHY IP has parameter setting for "Reference clock frequency for

10 GbE (MHz)" where user needs to specify whether you prefer PLL refclk input is 644MHz or 322MHZ

Whatever clock frequency that you provided in test bench design needs to match with the setting in Multirate PHY IP.

Can you double check your Multirate PHY IP setting again ?

Thanks.

Regards,

dlim