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ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

1/2.5/5/10G Multi-rate Ethernet PHY simulation cannot reach rx_block_lock

The simulation of the example design, provided by the "Low Latency Ethernet 10G MAC" IP, is running fine. However, when simulating my design, the PHY can not acheive rx_block_lock. The waveform sho...
Deshi_Intel's avatar
Deshi_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

I am able to duplicate the 322MHz example design sim run failure (rx_block_lock) stay low issue even in modelsim. While sim run with 644MHz setting is fine.

I am now consulting internally within Intel to figure out is this a bug or something that we miss out when using 322MHz setting.

Will keep you posted on status update

Thanks.

Regards,

dlim

ZWang142's avatar
ZWang142
Icon for New Contributor rankNew Contributor
5 years ago

Hi @DeshiL_Intel​ ,

There is a core_pll in models/tb_top.sv that also needs to be changed, as it uses refclk_10g as well.

After modifying this pll, the example design is able to run with refclk_10g at 322 MHz.

Now I'm checking what's wrong with my design...

Thanks.